Using PWM on LPC17xx

PWM can be used for generating analog signals of frequency very much lower than that of the PWM frequency. LPC1768 has one PWM with six channels. There will be one timer for each PWM and this timer will be used by all channels of that PWM. Configuring the PWM is similar to that of configuring a timer. The only difference is that we also need to specify the location of rising and falling edges for each channel that we use.

Follow the steps given below to configure the PWM as you wish.

1. Power up the PWM (LPC17xx manual table 46, pg 63). The PWM will be powered up when the microcontroller resets. So unless you have powered it down, there is need to follow this step.

LPC_SC->PCONP |= 1 << 6;

2. Setup and provide the clock to PWM peripheral (LPC17xx manual table 40 and 42, pg 56 and 57).

LPC_SC->PCLKSEL0 |= 1 << 12; // PWM clock = microcontroller clock i.e the prescaler value is 1.

3. Output pins of the microcontroller must be configured to select the PWM output pins. There is a Pin Control Module in LPC17xx which can be used to select the function of each pin and also it can be used to enable or disable the pull up and pull down registers. (LPC17xx manual table 83 and 91, pg 110 and 114)

LPC_PINCON->PINSEL4 |= 1 << 8; // P2.4 works as PWM1 output.

LPC_PINCON->PINMODE4 |= 1 << 9; // enable neither pull up nor pull down.

4. Set the rising and falling edge configurations as per your requirements.

 

There are 7 match registers associated with the PWM. By storing suitable values in these registers, desired waveform can be obtained. In this PWM we can control both the rising and falling edges. If we want to control both the edges then we need to use double edged control. Otherwise single edged control is sufficient. If we use double edged control then the number of channels that can be used simultaneously will be reduced, as each channel requires two match registers. In case of single edged PWM, match register MR0 is dedicated for the control of the rising edge of all channels and the remaining six match registers (MR1 to MR6) can be used to control the falling edge of the six channels. Since one of the match registers is required to store the PWM rate (MR0 in case of single edge control) only channels 2, 4 and 6 can be used simultaneously or channels 3 and 5 can be used simultaneously in case of double edge control. Channel one cannot be configured as double edged PWM when MR0 stores the value of PWM rate.

4a. Setting the rate of the PWM.

LPC_PWM1->MR0 = 16; // PWM freq = PWM clock/16

LPC_PWM1->MCR |= 1 << 1; // Reset timer on Match0 (LPC17xx manual table 449, pg 517)

The timer/counter associated with the PWM resets to ONE and not ZERO. Therefore if we need a PWM frequency of (PWM clock/N), then we need to store 'N' in one of the match registers and set the timer to reset on compare with that match register. Usually MR0 is used for this purpose. For single edge control only MR0 must be used to store PWM rate.

4b. For single edge PWM set the position of the falling edge.

In case of single edge control PWM, the PWM output will be high when the timer resets. Therefore we can control only the position of the falling edge. To control the falling edge of channel 'x', store the suitable compare value to MRx register.

LPC_PWM1->MR5 = 8;  // PWM Duty Cycle = 0.5

Here I am storing 8 in MR5. Therefore, now one cycle of PWM waveform consists of 16 PWM clock cycles and for 8 of them the PWM output will be high and for remaining 8 cycles it will be low. Therefore the effective signal produced is a waveform of frequency (PWM clock/16) with a duty cycle of 0.5.

4c. For double edge control (LPC17xx manual table 443, pg 512)

Table 443 of LPC17xx manual shows the match register pairs that are associated with each channel. By loading suitable values to these registers, desired waveform can be obtained. We have already set the PWM rate with the help of MR0 in 4a. Now to configure say, channel 4 we need to use MR3 and MR4.

LPC_PWM1->MR3 = 4;

LPC_PWM1->MR4 = 8;

The PWM output toggles on each compare match. If same value is stored in both the match registers, clear takes precedence and the PWM output will become LOW irrespective of its previous state.

5. Enable the timer/counter and PWM (LPC17xx manual table 447, pg 516)

LPC_PWM1->TCR |= (1 << 0) | (1 << 3);

6. Select control mode for each channel (except channel 1) and enable the PWM output (LPC17xx manual table 451, pg 519)

LPC_PWM1->PCR |= 1 << 4; // Configure channel 4 as double edge controlled PWM

LPC_PWM1->PCR |= 1 << 12; // Enable PWM channel 4 output

LPC_PWM1->PCR |= 1 << 13; //Enable PWM channel 5 output

7. Additional settings

Additional features like interrupt on a match compare or stopping the PWM on a match compare or resetting the PWM timer/counter on a match compare can all be done by playing with the PWM Match Control Resgister (PWM1MCR). Refer table 449, pg 517 of  the LPC17xx manual for further details.

8. Little more about interrupts

NVIC_EnableIRQ(PWM1_IRQn); // This will enable all interrupte pertaining to the PWM1

void PWM1_IRQHandler (void) 

{

}// This is the format in which the interrupt routine must be written

The source of the interrupt i.e to check which match compare caused the interrupt we can check the value of the interrupt flags in the PWM Interrupt Register (PWM1IR). The bit which is HIGH in this register corresponds to the source of that interrupt. The interrupt flag bit must be cleared before exiting the interrupt routine. Otherwise another interrupt will be serviced after completing the current interrupt. To clear the interrupt flag write '1' to that bit. Writing '0' will have no effect.

The complete compiled program that configures channel 4 as double edge control PWM and channel 5 as single edge control PWM and interrupts once in every PWM cycle is here.

I am using this PWM for the generation of sync pulses for TV and the motor control PWM for the generation of audio in the Game Console. More posts on actual Game Console implementation will be coming soon, after I explain every basic thing in LPC17xx that is required for the Game Console.